This invention relates to systems for performing frequency division of a high frequency signal with a very low level of power consumption, and in particular to a system for frequency division of a high frequency signal by employing intermittent operation of a phase lock loop, for use in a portable electronic timepiece.
At the present invention, there are various types of electronic devices of miniaturized portable type, such as electronic wristwatches and pocket calculators, for which the level of power consumption should be as low as possible, in order to ensure the maximum possible battery lifetime. Electronic wristwatches which are manufactured at present generally utilize complementary metal oxide silicon field effect transistor circuitry, which ensures a very low degree of power consumption. This is due to the fact that such devices have an extremely high impedance with respect to DC applied voltage when in the biased-off state. However, when such devices are used for switching, as in the case of the flip-flops in a frequency divider circuit for example, then as the frequency of operation is increased, the level of power consumption of the circuitry begins to increase sharply. For this reason, a major part of the power consumption of an electronic timepiece is due to the initial stages of frequency division of the high frequency output signal from the quartz crystal standard frequency oscillator circuit of the timepiece.
It is possible to operate these initial stages of frequency division in an intermittent manner, as will be described in the present disclosure, by producing a phase locked signal from a phase locked loop which is periodically locked into frequency and phase synchronism with the output of the initial frequency divider stages. After phase lock has been confirmed, the initial frequency divider stages are made inoperative, and the timekeeping circuits of the timepiece are supplied with the output signal from the variable frequency oscillator of the phase locked loop, either directly or through a frequency divider. After a predetermined period of time has elapsed, during which a slight degree of phase shift may have occurred in the signal from the variable frequency oscillator, the variable frequency oscillator is again locked into synchronism with the output signal from the initial stages of frequency division, which are again made operable at that time. However, it is difficult to implement such a system and to ensure reliable and precise operation, if a phase locked loop of conventional type is utilized. This is due to the fact that such a device does not actually provide continuous and exact phase lock with respect to the phase of a reference frequency. Instead, the phase of the signal from the variable frequency oscillator of a conventional phase lock loop cyclically varies with respect to the reference frequency phase. Over the long term, this variation in phase is generally unimportant for many applications. However, for the type of application toward which the present invention is directed, such as the frequency divider system of an electronic timepiece, it is essential to utilize a phase lock loop which provides exact phase lock.
Another disadvantage of a conventional type of phase lock loop is that it is often necessary to adjust the circuit so as to ensure that phase lock occurs at the desired reference frequency, and not at some harmonic or submultiple of the reference frequency. Providing automatic means for ensuring that phase lock occurs only at the reference frequency, for example when power is first switched on to the circuit, would be difficult and complex to implement with a conventional type of phase lock loop.
With a frequency divider system in accordance with the present invention, the above disadvantages of a conventional type of phase lock loop are eliminated. Precise locking into synchronism in phase and frequency with a reference frequency signal is ensured, without periodic variations in phase of the signal provided by the phase lock loop. In addition, recovery of phase lock in the event of temperary loss of lock due to a transient disturbance is accomplished rapidly and along an exponential curve with respect to time. Furthermore, means can be provided whereby an initial condition can be established after, for example, applying power to the circuit, whereby the signal provided by the phase lock loop becomes locked into synchronism in frequency and phase with the reference frequency in an automatic and reliable manner.